Kenji Yamamoto

Kenji Yamamoto spent twenty years as a process engineer at TSMC and Samsung before transitioning to semiconductor equity research. His hands-on experience with 7nm, 5nm, and 3nm node development gives him unparalleled insight into fab economics, yield curves, and the technical challenges facing chipmakers. Kenji holds a PhD in Materials Science from Tokyo Institute of Technology and has published extensively on gate-all-around transistor architectures and extreme ultraviolet lithography. He understands the intricate dance between chip designers, foundries, and equipment makers that drives this $500 billion industry. Kenji was among the first to recognize TSMC's insurmountable lead in advanced logic and correctly predicted the memory cycle bottom in 2022. His analysis goes beyond financial metrics to examine wafer start capacity, capex efficiency, and whether new fabs will generate acceptable returns. He tracks everything from ASML's EUV tool shipments to obscure specialty semiconductor companies most analysts ignore. Based in Hsinchu, Taiwan, Kenji maintains deep connections across Asia's semiconductor ecosystem while serving global investors seeking to navigate this technically complex, capital-intensive sector.